1. Field of the Invention
The present invention relates to a mask for adjusting transmittance of a light and a method for manufacturing the same. More particularly, the present invention relates to a mask having dummy features formed at peripheries of isolated edges of features corresponding to each circuit element of an integrated circuit to correct the optical proximity effect (OPE) and a method for manufacturing the same.
2. Description of the Related Art
As the minimum design rule of devices integrated in a semiconductor chip and connecting wires is reduced, a conventional lithography technique using an ultraviolet ray is not able to prevent distortion of a pattern formed in a wafer.
That is, although an i-ray and a deep ultraviolet ray (DUV ray) have wavelengths of 248 nm, a minimum design rule thereof is 190 nm, so distortion of the pattern is caused by diffraction and interruption of light during a semiconductor device manufacturing process.
The distortion of the pattern becomes more serious as the minimum design rule is reduced. Accordingly, correction is required for pattern distortion that occurs in a photolithography process due to a resolution limitation.
In a conventional photolithography process, a pattern of a photo mask is copied onto a wafer through an optical lens. Since an optical system for projecting an image acts as a low-band filter, the image formed on the wafer is distorted as compared with an original shape. When a rectangular-shaped mask is used, a circular pattern is formed on the wafer since the high-frequency light components do not pass through the edges of the rectangular-shaped mask. When the mask pattern is large, a basic spatial frequency is lowered, so the relatively high degree frequency may be transmitted through the mask, and the image formed on the wafer is substantially identical to the original image. However, when the pattern is small, the spatial frequency becomes high, so the transmission ratio is reduced and serious distortion occurs.
In an attempt to solve the problem described above, variations in lithography equipment have been developed, but these variations have limited effectiveness.
For this reason, an optical proximity correction (OPC) is suggested. According to optical proximity correction, the shape of the mask is pre-deformed, taking into consideration the distortion of the pattern, so that the image formed on the wafer is the desired image.
Optical proximity correction may be achieved when adjacent features are interacted with each other such that a pattern-dependent alteration is created. That is, lines designed to have the same dimensions and different proximities from other features have different dimensions from each other after the developing process has been finished. Accordingly, densely arranged lines are transcribed differently from more widely spaced lines. If the line width is not constant, serious problems may occur in an integrated chip.
In order to reduce the variation of a critical dimension (CD) caused by the optical proximity effect, a method for optimizing parameters of an exposure device and an OPC method are used.
First, the method for optimizing parameters of an exposure device is used to optimize a partial coherence and a numerical aperture (NA) of a lens. One conventional technique for reducing the CD by optimizing the NA is shown in FIG. 1. That is, the depth of focus (DOF) is proportional to a wavelength of a beam and inversely proportional to the NA, so the DOF is reduced as the NA is increased.
Second, as shown in FIGS. 2a to 2c, the OPC method using an auxiliary pattern having a resolution below the limit-resolution includes a HAMMER-HEAD method (FIG. 2a) for preventing the length of a pattern from being shortened, a SERIF method (FIG. 2b) for correcting an edge effect, and a BIAS method (FIG. 2c) for forming a bias pattern at an edge. Hatching areas shown in FIGS. 2a to 2c represent features that are transcribed onto the wafer to form the pattern.
The gradient of the isolated edge is adjusted such that it matches the edge intensity gradient of a densely packed edge by means of the additional lines. As a result, the isolated features are transcribed in the same manner as in the densely packed features so that the optical proximity effect is greatly reduced.
Various techniques for correcting the proximity effect using the above-mentioned auxiliary features in the form of bars have been studied and are used in the field. The auxiliary features and patterns are misconceived as a pattern fault so that a pattern defect is detected. However, when the shape of patterns on the mask is complicated, the created patterns are not able to match the design rule. In an extreme case, the singularity inspection by means of a design rule checking (DRC) is impossible.
A method for using a phase shift mask (PSM) has been suggested. The PSM exposes the pattern using interrupted light or an interrupted part, thereby increasing the resolution and the depth of focus. That is, when the patterns are repeatedly formed, the phase of the light radiated from left and right openings is shifted by 180 degrees such that the light intensity of a light shielding section formed between openings is set to zero, which is significantly different from the light intensity of the openings, thereby adjusting the light intensity.
Another method uses a transmittance adjustment mask. The transmittance adjustment mask is provided to increase fidelity and the depth of focus by adjusting the transmittance of the light at a part of a mask pattern.
The present invention has been made to solve the above-mentioned problems of the prior art. Therefore, it is a first feature of an embodiment of the present invention to provide a transmittance adjustment mask (TAM) having dummy features that adjust light passing through peripheries of features such that light intensities formed on wafer areas corresponding to edges of densely packed features are about the same as light intensities formed on other wafer areas corresponding to edges of isolated features.
A second feature of an embodiment of the present invention is to provide a method for manufacturing the transmittance adjustment mask of the present invention.
To provide the first feature of an embodiment of the present invention, there is provided a transmittance adjustment mask for optically transcribing a pattern corresponding to integrated circuits onto a semiconductor substrate by using an exposure device. The transmittance adjustment mask includes a plurality of features corresponding to circuit elements that form the integrated circuits, the plurality of features having predetermined minimum dimensions and having an isolated edge and a plurality of dense edges, and at least one semi-transparent dummy feature. The at least one semi-transparent dummy feature is spaced parallel and apart from the isolated edge by a predetermined distance such that a first light intensity in a first area of the semiconductor substrate, corresponding to the plurality of dense edges of the plurality of features, is about the same as a second light intensity in a second area of the semiconductor substrate, corresponding to the isolated edge of the plurality of features, wherein the at least one semi-transparent dummy feature has the predetermined minimum dimensions.
The dummy feature includes a semi-transparent material having a light transmittance that prevents the dummy feature from being transcribed onto the semiconductor substrate as a pattern.
The predetermined distance between the isolated edge of the plurality of features and the dummy feature is larger than the predetermined minimum dimension. Preferably, the isolated edge of the plurality of features is spaced apart from an adjacent edge by at least three times the predetermined minimum dimension.
A plurality of semi-transparent dummy features may be provided, wherein the plurality of dummy features are spaced apart from each other by the predetermined minimum distance.
According to another embodiment of the present invention, there is provided a transmittance adjustment mask for optically transcribing a pattern corresponding to integrated circuits onto a semiconductor substrate by using an exposure device. The transmittance adjustment mask includes a plurality of features corresponding to circuit elements that form the integrated circuits, the plurality of features having predetermined minimum dimensions and having a plurality of edges, wherein the plurality of edges include dense edges, which are closely adjacent to other edges, and isolated edges, which are remote from other edges. The transmittance adjustment mask also includes a plurality of dummy features installed on the transmittance adjustment mask and spaced parallel and apart from a corresponding isolated edge by a predetermined distance in order to adjust a light transmittance in peripheral areas of the isolated edges such that a first light intensity in a first area of the semiconductor substrate corresponding to the isolated edges is about the same as a second light intensity in a second area of the semiconductor substrate corresponding to the dense edges, wherein the plurality of semi-transparent dummy features have the predetermined minimum dimensions.
To provide the second feature of an embodiment of the present invention, there is provided a method for manufacturing a transmittance adjustment mask for optically transcribing a pattern corresponding to integrated circuits onto a semiconductor substrate using an exposure device. The method includes depositing a light shielding layer on a mask substrate, patterning the light shielding layer to form a plurality of features corresponding to circuit elements that form the integrated circuits having predetermined minimum dimensions, the plurality of features having a plurality of edges, wherein the plurality of edges includes dense edges closely adjacent to other edges and isolated edges remote from the other edges, depositing a semi-transparent transmittance adjusting layer on the mask substrate formed with the plurality of features, and patterning the semi-transparent transmittance adjusting layer to form a plurality of dummy features on the transmittance adjustment mask that are spaced parallel and apart from a corresponding isolated edge by a predetermined distance in order to adjust a light transmittance in peripheral areas of the isolated edges such that a first light intensity in a first area of the semiconductor substrate corresponding to the isolated edges is about the same as a second light intensity in a second area of the semiconductor substrate corresponding to the dense edges, wherein the plurality of semi-transparent dummy features have the predetermined minimum dimensions.
According to another embodiment of the present invention, there is provided a method for manufacturing a transmittance adjustment mask for optically transcribing a pattern corresponding to integrated circuits onto a semiconductor substrate by using an exposure device, the method includes depositing a semi-transparent transmittance adjusting layer on a mask substrate, patterning the semi-transparent transmittance adjusting layer to form a plurality of dummy features having predetermined minimum dimensions and having a plurality of edges, wherein the plurality of edges includes dense edges closely adjacent to other edges and isolated edges remote from other edges, depositing a light shielding layer on a mask substrate formed with the plurality of dummy features, and patterning the light shielding layer to form a plurality of features corresponding to circuit elements that form the integrated circuits, the plurality of features are spaced parallel and apart from a corresponding isolated edge of the plurality of dummy features by a predetermined distance in order to adjust a light transmittance in peripheral areas of the isolated edges such that a first light intensity in a first area of the semiconductor substrate corresponding to the isolated edges is about the same as a second light intensity in a second area of the semiconductor substrate corresponding to the dense edges, wherein the plurality of semi-transparent dummy features have the predetermined minimum dimensions.